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xro:beaglebone [2015-12-09 00:16]
xro
xro:beaglebone [2015-12-09 02:13] (current)
xro
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 Steps: Steps:
-- generate a new fb config, using ''​gtf <​width>​ <​height>​ <​refreshrate>​ -f''​ +  ​- generate a new fb config, using ''​gtf <​width>​ <​height>​ <​refreshrate>​ -f''​ 
-- add it to ''/​etc/​fb.modes''​ +  - add it to ''/​etc/​fb.modes''​ 
-- you're done, the rest happens automatically+  - you're done, the rest happens automatically
  
-<file txt  fb.modes.example>+== Example for Resolution 1440x900 == 
 + 
 +<file txt  fb.modes>​
 mode "​1440x900-60"​ mode "​1440x900-60"​
     # PCLK: 106.47 MHz, H: 55.92 kHz, V: 60.00 Hz     # PCLK: 106.47 MHz, H: 55.92 kHz, V: 60.00 Hz
Line 22: Line 24:
 endmode endmode
 </​file>​ </​file>​
 +
 +==== Rotating the BeagleBone Screen / Display ====
 +This can and should be done use X. Downside is you can't rotate the console like on the RPi.
 +Accomplish it using the ''​Rotate''​ X-Option of the Framebuffer Device.
 +
 +<file txt xorg.conf>​
 +Section "​Device"​
 +        Identifier ​     "​Builtin Default fbdev Device 0"
 +        Driver ​         "​fbdev"​
 +        Option ​ "​Rotate"​ "​CCW"​
 +EndSection
 +
 +Section "​Screen"​
 +        Identifier ​     "​Builtin Default fbdev Screen 0"
 +        Device ​         "​Builtin Default fbdev Device 0"
 +        DefaultDepth ​   16
 +EndSection
 +
 +Section "​ServerLayout"​
 +        Identifier ​     "​Builtin Default Layout"​
 +        Screen ​         "​Builtin Default fbdev Screen 0"
 +EndSection
 +</​file> ​
  
 ==== Transient State of pins during startup ==== ==== Transient State of pins during startup ====
 +
 +Basically, until the Device-Tree-Overlays are loaded, the Beageblone-Blacks gpio pins are in ''​INPUT''​ mode and sometimes, during bootup, may switch devices your relays and other stuff that depends on your pins being configured for ''​OUTPUT''​ at level 0, when powering up.
 +
 +There are two possible solution that I know of.
 +  - Don't power up your external gpio-controlled hardware before the BeagleBoneBlack has booted
 +  - Guard your GPIO Pins with some Peripheral-Buffer IC's that need an **EN**able signal.
 +
 +In both cases, you still need a pin to connect the EN signal or power-relay for our peripherals,​
 +a PIN that you can trust to pull your pheripheral LOW even during bootup.
 +
 +A good choice for that are most pins that, per default, are muxed not to the GPIOchips but to internal devices like UART, SPI, I2C.
 +
 +The following is a list of measurement,​ which pins pull which direction (HIGH/LOW) during bootup.
 +^PIN^ Test1 ^ Test2 ^ Test3 ^
 +|P8_01 | 0 (DGND) |||
 +|P8_02 | 0 (DGND) |||
 +|P8_03 | 1 | 1 ||
 +|P8_04 | 1 | 1 ||
 +|P8_05 | 1 | 1 ||
 +|P8_06 | 1 | 1 ||
 +|P8_07 | 1 | 1 ||
 +|P8_08 | 1 | 1 ||
 +|P8_09 | 1 | 1 ||
 +|P8_10 | 1 | 1 ||
 +|P8_11 | 0 | 0 ||
 +|P8_12 | 0 | 0 ||
 +|P8_13 | 0 | 0 ||
 +|P8_14 | 0 | 0 ||
 +|P8_15 | 0 | 0 ||
 +|P8_16 | 0 | 0 ||
 +|P8_17 | 0 | 0 ||
 +|P8_18 | 0 | 0 ||
 +|P8_19 | 0 | 0 ||
 +|P8_20 | 0 | 1 ||
 +|P8_21 | high freq signal, 0 |||
 +|P8_22 | float or high-freq, 1 |||
 +|P8_23 | 1 | 1 ||
 +|P8_24 | 1 | 1 ||
 +|P8_25 | PWM signal 1, floating? ||
 +|P8_26 | 1 | 1 ||
 +|P8_27 | 0 | 0 ||
 +|P8_28 | 1 | 0 ||
 +|P8_29 | 0 | 0 ||
 +|P8_30 | 0 | 0 ||
 +|P8_31 | 1 | 1 ||
 +|P8_32 | 1 | 0 ||
 +|P8_33 | 0 | 0 | 0 |
 +|P8_34 | 0 | 0 | 0 |
 +|P8_35 | 0 |||
 +|P8_36 | 0 |||
 +|P8_37 | 0 |||
 +|P8_38 | 0 |||
 +|P8_39 | 0 |||
 +|P8_40 | 0 |||
 +|P8_41 | 1 |||
 +|P8_42 | 1 |||
 +|P8_43 | 1 |||
 +|P8_44 | 1 |||
 +|P8_45 | 0 |||
 +|P8_46 | 0 |||
 +|P9_01 | 0 (DGND) |||
 +|P9_02 | 0 (DGND) |||
 +|P9_03 | 1 (3V3) |||
 +|P9_04 | 1 (3V3) |||
 +|P9_05 | 1 (VDD 5V) |||
 +|P9_06 | 1 (VDD 5V) |||
 +|P9_07 | 1 (SYS 5V) |||
 +|P9_08 | 1 (SYS 5V) |||
 +|P9_09 | PWR_BUT |||
 +|P9_10 | 1 (SYS_RESET) |||
 +|P9_11 | |||
 +|P9_12 | 1 |||
 +|P9_13 | 1 |||
 +|P9_14 | 0 |||
 +|P9_15 | pulsing 1 , every 480µs, floating? |||
 +|P9_16 | 0 | 0 ||
 +|P9_17 | 0 | 0 ||
 +|P9_18 | 1 | 0 ||
 +|P9_19 | 1 | 1 ||
 +|P9_20 | 1 | 1 ||
 +|P9_21 | 1 | 1 | 1 |
 +|P9_22 | 1 | 1 | 1 |
 +|P9_23 | 0 | 0 ||
 +|P9_24 | 1 | 1 ||
 +|P9_25 | 0 | 0 ||
 +|P9_26 | 1 | 1 ||
 +|P9_27 | 0 | 0 ||
 +|P9_28 | 0 | 0 ||
 +|P9_29 | 0 | 0 ||
 +|P9_30 | 0 | 0 ||
 +|P9_31 | 0 |||
 +|P9_32 | 1 (VDD_ADC) |||
 +|P9_33 | AIN4 |||
 +|P9_34 | 0 (GND_ADC) |||
 +|P9_35 | AIN6 |||
 +|P9_36 | AIN5 |||
 +|P9_37 | AIN2 |||
 +|P9_38 | AIN3 |||
 +|P9_39 | AIN0 |||
 +|P9_40 | AIN1 |||
 +|P9_41 | 0 | 0 ||
 +|P9_42 | 0 | 0 ||
 +|P9_43 | DGND |||
 +|P9_44 | DGND |||
 +|P9_45 | DGND |||
 +|P9_46 | DGND |||
  
  
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  • Last modified: 2015-12-09 00:16
  • by xro